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Ordering number: EN 5599
LC864332A/28A/24A/20A/16A/12A
CMOS LSI
LC864332A/28A/24A/20A/16A/12A 8-bit Single Chip Microcontroller
Overview
The LC864332A/28A/24A/20A/16A/12A microcontrollers are 8-bit single chip microcontrollers with the following on-chip functional blocks: * CPU : Operable at a minimum bus cycle time of 0.5 s * On-chip ROM maximum capacity : 32K bytes * On-chip RAM capacity : 384 bytes * CRT display RAM : 640 x 9 bits * Closed-caption TV controller and the on-screen display controller * 16-bit timer/counter * 4-channel x 5-bit A/D converter * 8-bit synchronous serial-interface circuit * Closed-caption data slicer * 12-source 10-vectored interrupt system All of the functions above are fabricated on a single chip.
Package Dimensions
unit : mm
3128-DIP52S
[LC864332A/28A/24A/20A/16A/12A]
52 27
15.2 13.8
1 46.0
26
5.1max
4.25
0.48
1.05
1.78
0.75
Feature
(1) Read-only memory (ROM) : LC864332A LC864328A LC864324A LC864320A LC864316A LC864312A 32768 x 8 bits 28672 x 8 bits 24576 x 8 bits 20480 x 8 bits 16384 x 8 bits 12288 x 8 bits
(2) Random access memory (RAM) :
384 x 8 bits 640 x 9 bits (for CRT display)
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters SANYO Electric Co., Ltd. Semiconductor LSI Div. Microcomputer Development Dep.
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
33098HA (II) No. 5599-1/20
0.51min
SANYO : DIP52S
3.8
0.25
LC864332A/28A/24A/20A/16A/12A
(3) OSD functions * Screen for display : 34 columns x 16 rows (at standard character size) * Display for RAM : 640 x 9 bits (6 columns for control + 34 columns for display) x 16 rows x 9 bits * 380 kinds of user specified characters Caption/Text mode : (9 x 9 dots) x 126 kinds OSD mode : (12 x 18 dots) x 254 characters (127 characters can also be used for Caption/Text mode) * Various character attributes Character colors : 16 colors Character background colors : 16 colors Fringe / shadow colors : 16 colors Full screen colors : 16 colors Fringe / shadow Rounding Underline Italic character (slanting) * Close-character attribute data changing available * Vertical display start line setting in row unit available (Row overlapping available) * Horizontal display start position setting available * Display mode specification by row (Display mode mixable) caption mode / text mode / OSD mode * Eight kinds of character size Horiz. x Vert. = (1 x 1), (1 x 2), (2 x 2), (2 x 4) (1.5 x 1), (1.5 x 2), (3 x 2), (3 x 4) * Shuttering and scrolling in row unit available * Horizontal pitch of character selectable : 9 to 16 dots * Polarity of R, G, B, I, BL output programmable * Polarity of HS, VS input programmable (4) Data slicer clock switching function Clock source can be selected from LC oscillation or CF (or Crystal) oscillation. (5) Bus cycle time / Instruction cycle time The LC864332A/28A/24A/20A/16A/12A microcontrollers are designed to read the ROM twice within one instruction cycle. It has about 1.7 times performance capability within the same instruction-cycle compared to our 4-bit microcontrollers (LC66000 series). The bus cycle time indicates the speed to read ROM.
Bus cycle time 0.49 s 7.5 s Instruction cycle time 0.99 s 15.0 s System clock oscillation Ceramic or Crystal Internal RC Oscillation frequency 12.08 MHz 800 kHz Supply voltage 4.5 V to 5.5 V 4.5 V to 5.5 V
(6) Ports - Input/output port Input/output port programmable in nibble units (When the N-ch open drain output is selected, bit-unit input is possible.) Input/output port programmable in a bit - Input ports (7) A/D converter - 4-channel x 5-bit A/D converter (Converted with program) (8) PWM output - 10-channel x 7-bit PWM
: 2 ports (16 lines) : 1 port (8 lines) : 1 ports (8 lines) : 2 ports (8 lines)
No. 5599-2/20
LC864332A/28A/24A/20A/16A/12A
(9) Timer - Timer 0 : 16-bit timer / counter 2-bit prescaler + 8-bit built-in programmable prescaler Mode 0 : Two 8-bit timers with a programmable prescaler Mode 1 : 8-bit timer with a programmable prescaler + 8-bit counter Mode 2 : 16-bit timer with a programmable prescaler Mode 3 : 16-bit counter The resolution of Timer is fixed to 1 tCYC. - Timer 1 : 16-bit timer / PWM Mode 0 : Two 8-bit timers Mode 1 : 8-bit timer + 8-bit PWM Mode 2 : 16-bit timer Mode 3 : Variable-bit PWM (9 to 16 bits) In Mode 0 and Mode 1, the resolution of Timer and PWM is tCYC. In Mode 2 and Mode 3, the resolution of Timer and PWM can be selected with program : tCYC or 1/2tCYC. (10) Remote-controlled receiver circuit (shares with the P73/INT3/T0IN terminal) - Noise rejection function - Polarity switching (11) Watchdog timer External RC circuit is required Interrupt or system reset is selectable (12) Interrupt system - 12-source 10-vectored interrupts: 1. External interrupt INT0 2. External interrupt INT1 3. External interrupt INT2, Timer/counter T0L (lower 8 bits) 4. External interrupt INT3 5. Timer/counter T0H (upper 8 bits) 6. Timer T1H, T1L 7. Serial interface 0 (SIO0) 8. Data slicer 9. Vertical synchronous signal interrupt (VS) 10. Port 0 - Interrupt priority control available Three interrupt priorities are supported (low, high and the highest) and multilevel nesting is possible. Low or high priority can be assigned to the interrupts from 3 to 10 listed above. To the external interrupt INT0 and INT1, high or the highest priority can be given. (13) Subroutine stack levels - A maximum of 128 levels (Set the stack inside a RAM) (14) Multiplication/division instruction - 16 bits x 8 bits ( 7-instruction cycle times) - 16 bits / 8 bits ( 7-instruction cycle times)
No. 5599-3/20
LC864332A/28A/24A/20A/16A/12A
(15) 3 oscillation circuits - On-chip RC ocscillation circuit for the system clock - On-chip CF oscillation circuit for the system clock - On-chip LC oscillation circuit for the CRT synchronization (16) Standby function - HALT mode function The HALT mode is used to reduce the power dissipation. In this mode, the program execution is stopped. This mode can be released by the interrupt request signal or the system reset. - HOLD Mode The HOLD mode is used to stop oscillations ; the RC (internal) and the ceramic oscillations. This mode can be released by the following operations. * Set the reset terminal (RES) to low level. * Feed the selected level to either P70/INT0 or P71/INT1. * Feed the Port 0 interrupt condition. (17) Factory shipment DIP52S (18) Development Tool - Evaluation chip - EPROM with a Window - One time ROM version - Emulator
: : : :
LC866098 LC86E4332 LC86P4332 EVA86000 (Main) + ECB864300 (Evaluation board) + POD864100 (Pod)
No. 5599-4/20
LC864332A/28A/24A/20A/16A/12A
System Block Diagram
Interrupt control
IR
PLA
ROM Standby control
CR RC LC
Clock Clock Generator generator
PC
Bus interface Bus Interface
ACC
SIO0
Port 1
B Register B register
Timer 0
Port 7
C Register C register
Timer 1
ALU
ADC INT0 3 INT0 to- INT3 Noise Rejection Filter Noise rejection filter
Port 9
Data slicer
PSW
PWM
PLL
RAR
OSD OSD control Control circuit Circuit
CGROM
RAM
Stack pointer Stack Pointer
VRAM Port 0
Watch Dog Timer Watchdog timer
No. 5599-5/20
LC864332A/28A/24A/20A/16A/12A
Pin Assignment
P10/SO0 P11/SI0/SB0 P12/SCK0 P13 P14 P15 P16 P17/PWM DVSS CF1 CF2 DVDD P90/AN0 P91/AN1 P92/AN2 P93/AN3 RES LC1 LC2 FILT AVDD AVSS CVIN VS HS I 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 P07 P06 P05 P04 P03 P02 P01 P00 P73/INT3/T0IN P72/INT2/T0IN P71/INT1 P70/INT0 PWM9 PWM8 PWM7 PWM6 PWM5 PWM4 PWM3 PWM2 PWM1 PWM0 BL B G R
Top view
No. 5599-6/20
LC864332A/28A/24A/20A/16A/12A
Pin Description
* Port option can be specified in bit units except the pull-up resistor selection of port 0. Pin Description Table
Pin name DVSS CF1 CF2 DVDD RES LC1 LC2 FILT AVDD AVSS CVIN VS HS I R G B BL PWM0 to PWM9 Port 0 P00 to P07 Pin No. 9 10 11 12 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 to 40 I/O -- Input Output -- Input Input Output Output -- -- Input Input Input Output Output Output Output Ouptut Output Function description Negative power supply for digital circuit Input terminal for ceramic resonator Output terminal for ceramic resonator Positive power supply for digital circuit Reset terminal LC oscillation circuit input terminal LC oscillation circuit output terminal Filter terminal for PLL Positive power supply for analog circuit Negative power supply for analog circuit Video signal input terminal Vertical synchronization signal input terminal Horizontal synchronization signal input terminal Image intensity output Red (R) output terminal of RGB image output Green (G) output terminal of RGB image output Blue (B) output terminal of RGB image output Fast blanking control signal Switch TV image signal and caption / OSD image signal PWM0 to 9 output terminal 15 V withstand 8-bit Input/output port Input/output can be specified in nibble units HOLD release input Interrupt input Pull-up resistor Provided/not provided (in bit units) Output Format CMOS/Nch-OD (in bit units) Output Format CMOS/Nch-OD (in bit units) Option
45 to 52
I/O
Port 1 P10 to P17
1 to 8
I/O
8-bit Input/output port Input/output can be specified in bit units. Other function P10 P11 P12 P17 SIO0 data output SIO0 data input / bus input / output SIO0 clock input / output Timrt 1 (PWM) output
Port 7 P70 P71 to P73
41 42 to 44
I/O Input
4-bit input port Other function INT0 input / HOLD release input / Nch-transistor output for watchdog timer P71 INT1 input / HOLD release input P72 INT2 input / timer 0 event input P73 INT3 input (noise rejection filter attached input) / timer 0 event input Interrupt receiver format vector address Rising INT0 INT1 INT2 INT3 enable enable enable enable Falling enable enable enable enable Rising/falling disable disable enable enable H level enable enable disable disable P70
Pull-up resistor provided/ not provided (in bit units)
L level enable enable disable disable
Vector 03H 0BH 13H 1BH
No. 5599-7/20
LC864332A/28A/24A/20A/16A/12A
Pin name Port 9 P90 to P93 13 to 16 Input Pin No. I/O 4-bit input port Other function AD converter input port (4 lines) Function Description Option
* Any port option can be selected in bit units. * Port 0 portion : Pull-up resistor is provided when CMOS output is selected. The pull-up resister is not provided when N-ch Open Drain is selected. * Port 1 option : Programmable pull-up resister is provided when any output form is selected.
* Port status during reset
Terminal Port 0 Port 1 Port 7 I/O Input Input Input Pull-up resistor status at selecting pull-up option Pull-up resistor OFF, ON after reset release Programmable pull-up resistor OFF Fixed pull-up resistor provided
* AVDD and AVSS are the power supply terminals for built-in analog circuit. DVDD and DVSS are the power supply terminals for built-in digital circuit. Connect them like the following figure to reduce the mutual noise-influence.
LSI Power supply Supply DVDD DVSS AVDD AVSS
No. 5599-8/20
LC864332A/28A/24A/20A/16A/12A
Specifications
1. Absolute Maximum Ratings at Ta=25C , VSS = 0 V
Parameter Symbol Pins Conditions VDD [V] Supply voltage Input voltage VDD max VI(1) DVDD, AVDD * P71, 72, 73 * Port 9 * RES, HS, VS, CVIN R, G, B, BL, I, FILT PWM0 to PWM9 Ports 0, 1, P70 Ports 0, 1 * Pull-up MOS transistor output * At each pin * CMOS output * At each pin * CMOS output * At each pin The total of all pins The total of all pins The total of all pins At each pin At each pin At each pin The total of all pins The total of all pins The total of all pins The total of all pins Ta = -30 to +70C -30 -55 DVDD = AVDD min -0.3 -0.3 Ratings typ max +7.0 VDD+0.3 V Unit
Output voltage
VO(1) VO(2)
-0.3 -0.3 -0.3 -2
VDD+0.3 +15 VDD+0.3 mA
Input/output voltage Highlevel output current Peak output current
VIO IOPH(1)
IOPH(2) IOPH(3) Total output current IOAH(1) IOAH(2) IOAH(3) IOPL(1) IOPL(2) IOPL(3) Total output current IOAL(1) IOAL(2) IOAL(3) IOAL(4)
Ports 0, 1 R, G, B, BL, I Port 1 Port 0 R, G, B, BL, I Ports 0, 1 P70 * R, G, B, BL, I * PWM0 to PWM9 Port 0 Port 1, P70 R, G, B, BL, I PWM0 to PWM9 DIP52S
-4 -5 -10 -10 -15 20 30 5 40 40 15 30 430 +70 +150 mW C
Lowlevel output current
Peak output current
Maximum power dissipation Operating temperature range Storage temperature range
Pd max Topr Tstg
* DVSS and AVSS must be supplied the same voltage, VSS. DVDD and AVDD must be supplied the same voltage, VDD.
VSS = DVSS = AVSS VDD = DVDD = AVDD
No. 5599-9/20
LC864332A/28A/24A/20A/16A/12A
2. Recommended Operating Range at Ta = -30C to +70C, VSS = 0 V
Parameter Symbol Pins Conditions VDD [V] Operating supply voltage range Hold voltage VDD VHD DVDD, AVDD DVDD, AVDD 0.97 s tCYC tCYC 1.02 s RAMs and the registers hold data at HOLD mode. Output disable Output disable 4.5 to 5.5 4.5 to 5.5 min 4.5 2.0 Ratings typ max 5.5 5.5 V Unit
Input high-level voltage
VIH (1) VIH (2)
Port 0 (Schmitt) * Port 1 (Schmitt) * P72, 73 * HS, VS * P70 port input / interrupt * P71 * RES (Schmitt)
0.6V DD 0.75V DD
VDD VDD
VIH (3)
Output N-channel transistor OFF
4.5 to 5.5
0.75V DD
VDD
VIH (4) VIH (5) Input low-level voltage VIL (1) VIL (2)
P70 Output N-channel Watchdog timer input transistor OFF Port 9 port input Port 0 (Schmitt) Output disable Output disable
4.5 to 5.5 4.5 to 5.5 4.5 to 5.5 4.5 to 5.5
VDD-0.5 0.7V DD VSS VSS
VDD VDD 0.2VDD 0.25V DD
* Port 1 (Schmitt) * P72, 73 * HS, VS * Port 9 * P70 port input / interrupt * P71 * RES (Schmitt)
VIL (3)
N-channel transistor OFF
4.5 to 5.5
VSS
0.25V DD
VIL (4) VIL (5) CVIN input amplitude Operation cycle time VCVIN tCYC(1) tCYC(2)
P70 N-channel transistor Watchdog timer input OFF Port 9 port input CVIN OSD function Except OSD function
4.5 to 5.5 4.5 to 5.5 5.0 4.5 to 5.5 4.5 to 5.5
VSS VSS 1Vp-p 1Vp-p -3dB 0.97 0.97 1
0.6VDD 0.3VDD 1Vp-p +3dB 1.02 40 Vp-p s *
* Vp-p : Peak-to-peak voltage
No. 5599-10/20
LC864332A/28A/24A/20A/16A/12A
Parameter Symbol Pins Conditions VDD [V] Oscillation frequency range (Note 1) FmCF(1) CF1, CF2 12 MHz (ceramic resonator oscillation) Refer to Figure 1. 12.08 MHz (ceramic resonator oscillation) Refer to Figure 1. LC1, LC2 14.11 MHz (LC oscillation) Refer to Figure 2. RC oscillation CF1, CF2 12 MHz (ceramic resonator oscillation) Refer to Figure 3. 12.08 MHz (ceramic resonator oscillation) Refer to Figure 3. 4.5 to 5.5 4.5 to 5.5 min 11.76 Ratings typ 12 max 12.24 MHz Unit
FmCF(2)
11.84
12.08
12.32
FmLC
14.11
FmRC Oscillation stable time period (Note 2) tmsCF(1)
4.5 to 5.5 4.5 to 5.5
0.3
0.8 0.02
2.0 0.2 ms
tmsCF(2)
0.02
0.2
(Note 1) Refer to Table 1 and 2 for the oscillation constant. (Note 2) The oscillation stable time is a period necessary for the oscillation to be stable after the power first applied, the HOLD mode released the main-clock oscillation stop instruction released. Refer to the Figure 3 for details.
No. 5599-11/20
LC864332A/28A/24A/20A/16A/12A
3. Electrical Characteristics at Ta = -30C to +70C , VSS = 0 V
Parameter Symbol Pins Conditions VDD [V] Input high-level current IIH(1) * Port 1 * Port 0 without pull-up MOS transistor * Output disable * Pull-up MOS transistor OFF * VIN = VDD (including the off-leak current of the output transistor) VIN = VDD 4.5 to 5.5 min Ratings typ max 1 A Unit
IIH(2)
* Port 7 without pull-up MOS transistor * Port 9 * RES * HS, VS * Port 1 * Port 0 without pull-up MOS transistor
4.5 to 5.5
1
Input low-level current
IIL(1)
* Output disable * Pull-up MOS transistor OFF * VIN = VSS (including the off-leak current of the output transistor) VIN = VSS
4.5 to 5.5
-1
IIL(2)
* Port 7 without pull-up MOS transistor * Port 9 * RES * HS, VS CMOS output of ports 0, 1 R, G, B, BL, I Ports 0, 1 Ports 0, 1
4.5 to 5.5
-1
IIL(3) Output high-level voltage VOH(1) VOH(2) Output low-level voltage VOL(1) VOL(2)
VIN = VSS IOH = -1.0 mA IOH = -0.1 mA IOL = 10 mA * IOL = 1.6 mA * The total current of the ports 0, 1 is 40 mA or less. * IOL = 3.0 mA * The current of any unmesured pin is 3 mA or less. IOL = 1 mA VOH = 0.9 VDD
4.5 to 5.5 4.5 to 5.5
-1 VDD-1 V
4.5 to 5.5 VDD-0.5 4.5 to 5.5 4.5 to 5.5 1.5 0.4
VOL(3)
* R, G, B, BL, I * PWM0 to PWM9
4.5 to 5.5
0.4
VOL(4) Pull-up MOS transistor resistance Output off-leakage current Hysteresis voltage Rpu
P70 * Ports 0, 1 * Port 7 PWM0 to PWM9 * Ports 0, 1 * Port 7 * RES * HS, VS
4.5 to 5.5 4.5 to 5.5 13 38
0.4 80 k
IOFF VHIS
VOUT = 13.5 V Output disable
4.5 to 5.5 4.5 to 5.5 0.1VDD
5
A V
No. 5599-12/20
LC864332A/28A/24A/20A/16A/12A
Parameter Symbol Pins Conditions VDD [V] Input clamp voltage Pin capacitance VCLMP CP CVIN All pins * f = 1MHz * Unmeasured terminals for the input are set to VSS level. * Ta = 25C 5.0 4.5 to 5.5 min 2.3 Ratings typ 2.5 10 max 2.7 V pF Unit
4. Serial Input/Output Characteristics at Ta = -30C to +70C , VSS = 0 V
Parameter Symbol Pins Conditions VDD [V] Cycle Low level pulse width High level pulse width Cycle Output clock Low level pulse width High level pulse width tCKCY(1) tCKL(1) * SCK0 * SCLK0 Refer to Figure 5. 4.5 to 5.5 min 2 1 Ratings typ max tCYC Unit
Input clock
tCKH(1)
1
Serial clock
tCKCY(2) tCKL(2)
* SCK0 * SCLK0
* Use an external pull-up resistor (1 k) when an open drain output * Refer to Figure 5.
4.5 to 5.5
2 1/2tCKCY
tCKH(2)
1/2tCKCY
Serial input
Data set-up time Data hold time Output delay time (External serial clock) Output delay time (Internal serial clock)
tICK tCKI tCKO(1)
* SI0
* Set to the rise of SCK0 * Refer to Figure 5.
4.5 to 5.5 4.5 to 5.5
0.1 0.1 7/12tCYC +0.2
s
* SO0
Serial output
tCKO(2)
* Use an external 4.5 to 5.5 pull-up resistor (1 k) when an open drain output. * Set to the fall of 4.5 to 5.5 SCK0 * Refer to Figure 5.
s
1/3tCYC +0.2
No. 5599-13/20
LC864332A/28A/24A/20A/16A/12A
5. Pulse Input Conditions at Ta = -30C to +70C, VSS = 0 V
Parameter Symbol Pins Conditions VDD [V] High/low level pulse width tPIH(1) tPIL(1) tPIH(2) tPIL(2) * INT0, INT1 * INT2/T0IN INT3/T0IN (The noise rejection clock is set to 1/1) INT3/T0IN (The noise rejection clock is set to 1/16) RES HS, VS * Interrupt acceptable * Timer0-countable * Interrupt acceptable * Timer0-countable 4.5 to 5.5 4.5 to 5.5 min 1 2 Ratings typ max tCYC Unit
tPIH(3) tPIL(3)
* Interrupt acceptable * Timer0-countable
4.5 to 5.5
32
tPIL(4) tPIH(5) tPIL(5)
Reset acceptable Display position controllable Each active edge of HS, VS must be more than 1tCYC. Refer to Figure 7. Refer to Figure 7. The monitor point in Figure 10 is 1/2 VDD.
4.5 to 5.5 4.5 to 5.5
200 10
s tCYC
Rising/falling time Horizontal pull-in range
tTHL tTLH FH
HS HS
4.5 to 5.5 4.5 to 5.5 15.23 15.73
500 16.23
ns kHz
6. A/D Converter Characteristics at Ta = -30C to +70C, VSS = 0 V
Parameter Symbol Pins Conditions VDD [V] Resolution Absolute precision Conversion time N ET tCAD (Note 3) From Vref selection to when the result is output 1 bit conversion time = 2tCYC (Regulate the ladder resistor) AN0 to AN3 VAIN = VDD VAIN = VSS 4.5 to 5.5 4.5 to 5.5 4.5 to 5.5 min Ratings typ 5 1/4 2 3/4 max bit LSB s Unit
Reference current Analog input voltage range Analog port input current
IREF VAIN IAINH IAINL
4.5 to 5.5 4.5 to 5.5 4.5 to 5.5 4.5 to 5.5 -1 VSS
1.0
2.0 V DD 1
mA V A
(Note 3) Absolute precision excepts quantizing error (1/2 LSB).
No. 5599-14/20
LC864332A/28A/24A/20A/16A/12A
7. Current Drain Characteristics at Ta = -30C to +70C , VSS = 0 V
Parameter Symbol Pins Conditions VDD [V] Current drain during basic operation (Note 4) IDDOP(1) DVDD, AVDD * FmCF = 12 MHz or FmCF = 12.08 MHz When ceramic resonator oscillation * FmLC = 14.11 MHz When LC oscillation * System clock : CF oscillation * Internal RC oscillation stops * HALT mode * FmCF = 12 MHz or FmCF = 12.08 MHz When ceramic resonator oscillation * FmLC = 0 Hz (When oscillation stops) * System clock : CF oscillation * Internal RC oscillation stops. * HALT mode * FmCF = 0 MHz (When oscillation stops) * FmLC = 0 Hz (When oscillation stops) * System clock : Internal RC * HOLD mode * All oscillation stops. 4.5 to 5.5 min Ratings typ 16 max 28 mA Unit
Current drain in HALT mode (Note 4)
IDDHALT(1)
DVDD, AVDD
4.5 to 5.5
5
10
mA
IDDHALT(2)
DVDD, AVDD
4.5 to 5.5
600
1200
A
Current drain in HOLD mode (Note 4)
IDDHOLD
DVDD, AVDD
4.5 to 5.5
0.05
20
A
Note 4 :
The currents to the output transistors and the pull-up MOS transistors are ignored.
No. 5599-15/20
LC864332A/28A/24A/20A/16A/12A
Oscillation types 12 MHz ceramic resonator oscillation Manufacturer Murata Oscillator CSA12.0MTZ CST12.0MTW Kyocera 12.08 MHz ceramic resonator oscillation Murata Kyocera KBR-12.0M CSA12.0MTZ021 KBR-12.08M 33 pF 33 pF 33 pF C1 33 pF on chip 33 pF 33 pF 33 pF C2 33 pF
* Both C1 and C2 must use a K rank (10%) and SL characteristics. Table 1. Ceramic Resonator Oscillation Guaranteed Constant (main-clock)
Oscillation type 14.11 MHz LC oscillation
L 4.7 H 4.7 H 10% (Variable)
C3 33 pF 33 pF
C4 45 pF (Trimmer) 33 pF
* See Figures 11 and 12. Table 2. (Notes) LC oscillation Guaranteed Constant (OSD clock) * * * Since the circuit pattern affects the oscillation frequency, place the oscillation-related parts as close to the oscillation pins as possible with the shortest pattern length. If you use other oscillators than those shown above, we provide no guarantee for the characteristics. Adjust the voltage of monitor point in figure 10 to 1/2 VDD 10% by the LC oscillation constant 'L' or 'C' to lock the PLL circuit.
Figure 1
Main clock Ceramic Resonator Oscillation
OSD clock Figure 2 LC Resonator Oscillation
No. 5599-16/20
LC864332A/28A/24A/20A/16A/12A
VDD VDD VDD lower limit VDD limit 0V 0V
Power supply Reset time RES Internal RC resonator oscillation tmsCF CF1, CF2
Operation mode
Unfixed
Reset
Instruction execution mode
< Reset time and oscillation stable time. > HOLD release signal Valid
Internal RC resonator oscillation tmsCF CF1, CF2
Operation mode
HOLD
Instruction execution mode
< HOLD release signal and oscillation stable time. >
Figure 3 Oscillation Stable Time
VDD VDD RRES RES CRES
(Note) Set the values of CRES, RRES so that the reset time is 200 s or longer.
(Note) Fix value of CRES, RRES that is sure to reset untill 200 s, after Power supply has been over inferior limit of supply voltage.
Figure 4 Reset Circuit No. 5599-17/20
LC864332A/28A/24A/20A/16A/12A 0.5VDD 0.5VDD < AC timing point >
tCKCY tCKL Serial clock tICK Serial input tCKO Serial output < Timing >
Figure 5 Serial Input/output Test Condition
VDD tCKH 1K tCKI
50pF
< Test load >
tPIL
tPIH
Figure 6 Pulse Input Timing Condition - 1
tPIL (5)
0.75VDD 0.75VDD 0.75VDD 0.25VDD
tPIH (5)
0.75VDD 0.75VDD 0.25VDD 0.75VDD
tTLH
tTLH t
tPIL (5)
1tCYC
1tCYC
(a) In case of active low
(b) In case of active high
Figure 7 Pulse Input Timing Condition - 2 LC864300
10 k HS HS C536
Figure 8 Recommended Interface Circuit No. 5599-18/20
LC864332A/28A/24A/20A/16A/12A
Noise filter 470
C-Video
560 pF 2.2 F
CVIN
Coupling capacitor
Figure 9 CVIN Recommended Circuit
Monitor point 22 k
FILT + 2.2 F 1000 pF
Figure 10 FILT Recommended Circuit
(Note) * Place the parts connected FILT terminal as close to the FILT as possible with the pattern length on the board.
16
VDD = 5.0V VVDD 5.0V = DD 4.7H LL==4.7H C = C1 = C2 C = C3 = C4 Ta = 25C Ta = 25C
16
C = 30pF C = 33pF C = 36pF
VDD = 5.0V VDD VDD = = C2 = 33pF C1 5.0V Ta C3 = = 25C C4 = 33pF Ta = 25C
L = 4.5H
15
15
L = 4.7H L = 4.9H L = 5.1H
14
C = 39pF
14
13
13
0
1
2
3
4
5
0
1
2
3
4
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Figure 11 FILT-LC Oscillation Frequency(1)
Figure 12 FILT-LC Oscillation Frequency(2)
No. 5599-19/20
LC864332A/28A/24A/20A/16A/12A
No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. Anyone purchasing any products described or contained herein for an above-mentioned use shall: Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of March, 1998. Specifications and information herein are subject to change without notice.
PS No. 5599-20/20

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